I2C Master Implementation in Verilog - Part 3

Continuation from part 2.5...
So I've learned that making a bidirectional port isn't as hard as I thought. After declaring SDA as an inout, I would use this assign statement:
assign SDA = (SDAinout) ? 1'bz : dataOut; Now, whenever SDAinout is 1'b1, SDA becomes in input, and when SDAinout is 1'b0, SDA becomes an output (dataOut). I don't remember which forum I found this information but a quick search on Google yielded many results.

Continuing with the rest of the project...
Since the data on SDA has to be valid by the time SCL is high, I first tried making a sepparate clock that is two times faster than SCL. This way there would be a clock edge present at the middle the negative level of SCL as well as at SCL. I quickly realized that by doing this, I would need to trigger SDA and SCL at different clock edges as shown in the picture. To make things more simple, I decided to use a clock that is four times faster than SCL so that the center point and the start of SCL can both be clocked with the positive edge.

Now, using this 4xSCL clock, I have created several routines which handle the start/stop, address/register sending as well as the data sending.

My last step is to create a state machine that ties all of the routines together and the project is finished.