I2C Master Implementation in Verilog - Part 2

After reading on the basics of the I2C protocol, I drew a flow chart to try and map my understanding. The left half shows the Master Read routine and the right shows the Master Write routine.

One part I was unsure about was that if the slave would send an ACK signal after it receives a valid register address. The single master I2C tutorial on best-microcontroller-projects.com shows that there is such an ACK signal but other resources do not mention this.

Another part of the protocol which is unclear to me is what data should I have in SDA when I send the ACK bit. I assume that D0-D7 are don't cares when checking for ACK, so for now I will send all zeros.


Whats next?...

• Start creating the verilog modules for an I2C Master including:
  -Start/Stop signal generator
  -Shift Registers for parallel to serial/serial to parallel functionality
  -ACK signal detector (probably not a separate module)
  -Clock divider (50MHz to 100kHz for SCLK)
  
  
  

I2C Master Implementation in Verilog - Part 1

From today, I will post on my progress on writing an I2C Master implementation in Verilog on my Xilinx Spartan 3E FPGA board.
I will be using the I2C master to read time and date data from a Maxim DS1337 Real Time Clock.

I have used this particular RTC before for my senior design project, but I had simply used a preexisting library on an Arduino with the I2C implementations specific to the RTC.

Here is a list of references I have found that may be useful:

• http://www.robot-electronics.co.uk/acatalog/I2C_Tutorial.html
• http://www.best-microcontroller-projects.com/i2c-tutorial.html
• http://datasheets.maxim-ic.com/en/ds/DS1337-DS1337C.pdf
  

Whats next?...

• Draw a flow chart mapping the design
• Re-familiarize myself in the Xilinx ISE Suite