I2C Master Implementation in Verilog - Part 2

After reading on the basics of the I2C protocol, I drew a flow chart to try and map my understanding. The left half shows the Master Read routine and the right shows the Master Write routine.

One part I was unsure about was that if the slave would send an ACK signal after it receives a valid register address. The single master I2C tutorial on best-microcontroller-projects.com shows that there is such an ACK signal but other resources do not mention this.

Another part of the protocol which is unclear to me is what data should I have in SDA when I send the ACK bit. I assume that D0-D7 are don't cares when checking for ACK, so for now I will send all zeros.


Whats next?...

• Start creating the verilog modules for an I2C Master including:
  -Start/Stop signal generator
  -Shift Registers for parallel to serial/serial to parallel functionality
  -ACK signal detector (probably not a separate module)
  -Clock divider (50MHz to 100kHz for SCLK)