I2C Master Implementation in Verilog - Part 5

The coding is done and it compiled with no errors. The next step is to create a testbench...

I2C Master Implementation in Verilog - Part 4 mini

Started testing all of my modules, I haven't used Xilinx ISE in a while so I didn't have ModelSim for Xilinx but i used ModelSim Altera Edition and it worked fine.

The start signal module seems to work fine:


The stop signal module works as planned as well:


The address signal is working well also:
(sent address as 8'b11010000) 0th bit is RW bit


more to come...